1. Field of the Invention
The present invention generally relates to semiconductor integrated device design and fabrication and, more particularly, to techniques for improving self aligned contact (SAC) fabrication in ULSI memory arrays such as dynamic random access memories (DRAM).
2. Description of the Related Art
An insulated gate field-effect transistor (FET) is made from a silicon wafer using state-of-the-art semiconductor processing techniques. Typically these FET's are comprised of a conductively doped polycrystalline silicon gate electrode, a thin gate dielectric lying under the gate electrode, and a pair of source/drain regions formed in the silicon wafer body.
The source and drain regions are separated from each other by a channel region that lies below the gate dielectric (oxide). The source/drain regions are typically created using an ion implantation doping technique in which the gate electrode itself is conveniently used as an implantation mask to prevent unwanted doping of the channel region. In this respect, in order to avoid an electrical short between the source and the drain regions, the channel region should be free of dopant atoms. Additionally, having insulating sidewall-spacers along the sidewalls of the gate electrode may also provide a better implantation shield for the channel region. These spacers increase the initial lateral separation between the source/drain regions which in turn prevents an undesirable overlap between the gate electrode and the source/drain regions.
Once the source/drain regions have been implanted and the gate electrode structure has been formed, the source and drain must then be electrically connected to the circuit. Typically, a source/drain contact metallization process, i.e., deposition of conductive contacts, must be done to form the contacts for these source/drain regions. However, this is not an easy task in the semiconductor industry. A contact metallization process requires that a patterned masking layer or layers be used to expose the contact openings of the underlying device structures while protecting surrounding devices from the unwanted effects of etching and depositing materials. Typically, self aligned contact processes are used to expose the contact openings. These processes use the selective etchability of the different layers to allow for less precise alignment of the masks to thereby expose the contact regions. In the past, using conventional lithographic techniques, mask alignment tolerances and the contact metallization process itself have significantly limited both the degree of simplification and the degree of chip size reduction that could be attained. Self-aligned contact opening technologies in general help to alleviate limitations set by mask alignment tolerances.
Self-aligned contact (SAC) fabrication technology uses a selective etching process to etch a contact opening through a masking layer or layers along the upper surfaces of the source/drain regions. It is understood that commonly used materials, such as silicon nitride, silicon oxide, silicon, polysilicon and photoresist all have different etch removal rates when exposed to various etchants. The boundaries of the contact openings are determined by the etch rate difference between the spacer material (e.g., silicon nitride), and the masking material (e.g., silicon oxide). Specifically, the spacer has a slower etch rate than the oxide so that the contact opening can be defined by using an etchant that will quickly remove the masking material but not have such a great effect on the spacer. Hence, the photoresist pattern that is used to define the contact opening need not be precisely aligned with the active area. In other words, the opening defined by the resist mask may be wider than the active area to which contact must be made. Consequently, this makes the SAC technique very attractive for ULSI applications where small device dimensions require very tight masking tolerances.
An exemplary prior-art SAC fabrication process can be seen in FIGS. 1A through 1D. In FIG. 1A, an exemplary pair of gate stack structures 102 is located on the surface of a silicon substrate 100 and define a source/drain region 104. Further, as seen in FIG. 1A, both of the gate stack structures have a polysilicon core (layer) 106 surrounded by a pair of nitride sidewall spacers 108 and a nitride top spacer 110. As a first step in the SAC opening process, the circuitry shown in FIG. 1A is covered with a silicon oxide layer 111 (FIG. 1B) and a photoresist layer 112 (FIG. 1C). The photoresist layer 112 is then patterned to thereby expose the oxide layer 111 and to define contact holes 116 (FIG. 1D). Through openings 114 in the photoresist layer, the underlying silicon oxide 111 is selectively etched to form a contact hole 116 in the silicon oxide 111 (FIG. 1D). Etchants used in this process must be selective to nitride, silicon and photoresist. That is, etchants selectively leave nitride spacers while etching away silicon oxide.
However, conventional SAC technology presents some problems due to its strict dependence on the selectable etchability of the materials. As seen in the prior art example given above, due to the use of silicon oxide masking layers, nitride becomes an irreplaceable material for spacer structures. However, silicon oxide, for example, possesses many advantageous features over nitride material as a spacer material. Some of these advantages are simplified processing and soft dielectric characteristics of the silicon. Additionally, oxide spacers induce less stress over the substrate and the neighboring gate stack layers, as compared to nitride spacers. As is well known in the art, nitride is a rigid and brittle material. When deposited on materials having less rigidity, the nitride increases the stress level in the neighboring materials and hence causes stress induced defects.
Another problem with the conventional SAC is the requirement of using an etching process very selective to nitride. In deep sub-half micron ULSI conditions, however, this is almost impossible. Even with costly equipment and highly selective processes, there is always some amount of etching in the nitride spacers 108, 110. Since the depth of the oxide layer 111 is much greater over the substrate than over the spacers 108, 110, the spacers are exposed to the etchants for a long time before the substrate 200 is exposed. Accordingly, even highly selective etchants will consume some of the spacers 108, 110. As discussed above, the spacers 108, 110 not only protect the polysilicon gate from the etchants, they also provide electrical isolation between the gate and the contact region. Therefore, for very small device dimensions, even a small amount of etching of the spacers can increase the likelihood of an electrical short between the gate electrode and the conductive contact material.